IEC 62050 Ed. 1.0 en – VHDL Register Transfer Level (RTL) synthesis
Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.
Product Details
- Edition:
- 1.0
- Published:
- 07/19/2005
- Number of Pages:
- 121
- File Size:
- 1 file , 790 KB
- Note:
- This product is unavailable in Ukraine, Russia, Belarus
